74HC73 - Dual JK flip-flop with reset

74HC73 - Dual JK flip-flop with reset; negative-edge trigger

Description:

The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A.

The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.

The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.

The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features:

• Low-power dissipation
• Complies with JEDEC standard no. 7A
• ESD protection:
  • HBM EIA/JESD22-A114-B exceeds 2000 V
  • MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from -40 °C to +80 °C and from -40 °C to +125 °C.

*Image shown is a representation only.